The subject matter described herein is concerned with semiconductor devices and methods for fabricating the same. In particular, the subject matter described herein relates to a dynamic random access memory (DRAM) device having dual-gate vertical channel transistors and a method of fabricating the same.
A unit cell of a general semiconductor memory device is comprised of a single transistor and information storage. For example, a DRAM unit cell has a single capacitor as the information storage, while a flash memory unit cell has a floating gate. A static RAM cell uses a flip-flop circuit as the information storage.
There are arising various technical problems along with an increase in integration density of semiconductor devices. I particular, the shrinking-down of DRAMs in dimension makes it more difficult to assure sufficient electrostatic capacitance. Accordingly, an architecture of a DRAM that uses a semiconductor substrate (i.e., bulk) as a storage node without a capacitor has been proposed. The capacitorless DRAM is advantageous in simplicity of fabrication because it does not need the processes for making a capacitor, as well in reducing unit cell area. There is disclosed an exemplary technique for the capacitorless DRAM in U.S. Pat. No. 6,548,848 by Fumio Horiguchi, entitled, “Semiconductor Memory Device.”
Such a capacitorless DRAM employs variation of threshold voltage by excessive holes present in a semiconductor substrate, being schematically classified into a single-gate structure using an SOI (silicon-on-insulator) substrate, and a dual-gate structure using a substrate interposed between two gate electrodes. According to the inquiry by T. Tanaka (“Scalability Study on Capacitorless IT-DRAM: From Single-gate PD-SOI to Double-gate FinDRAM”, IEDM, 2004), the single-gate structure is required to have a gate width over 100 nm because it is sensitive to effects of shortening retention time and fluctuating threshold voltage. The single-gate structure with gate width over 100 nm is basically needed to increase impurity concentration of the channel in order to prevent a short channel effect. However, increasing impurity concentration in the channel is accompanied by an increase of leakage current, resulting in a decrease of retention time. Further, since such reduction of gate width decreases the number of charges stored in the SOI substrate, a fluctuation of the threshold voltage increases.
Because of the restriction on gate width in the single-gate structure, dual-gate structures have been suggested as new-generation DRAMs with high integration density. However, as general dual-gate DRAMs are adopting the features that source and drain regions are arranged horizontally with each other, there is a limit to scaling down a chip size. For instance, the former article by Tanaka shows layout efficiency of 9F2 (‘F’ means the least line width scalable by a photolithography process) for DRAM architecture, which is regarded as being inefficient rather than a NAND flash memory. Whereas there are proposed various techniques for enhancing the layout efficiency, those techniques result in high manufacturing costs due to complicated processing steps.